A Decode Error (DECERR) in AXI indicates that a transaction address does not map to a valid subordinate device in the system.
Understanding AXI Decode Errors (DECERR)
In the Advanced eXtensible Interface (AXI) protocol, system components like processors (managers/masters) communicate with peripherals or memory (subordinates/slaves) via an interconnect. Each subordinate device is assigned a specific address range.
A decode error, signaled by DECERR, occurs when a manager initiates a transaction (read or write) to an address for which there is no subordinate device connected to the interconnect.
Key Points about DECERR
- Generation Source: DECERR is often generated by an interconnect component. The interconnect is responsible for decoding the address provided by the manager and routing the transaction to the correct subordinate. If the address falls outside the address ranges of all connected subordinates, the interconnect asserts the DECERR response.
- Cause: The primary cause is attempting to access an unmapped or invalid memory/peripheral address.
- Significance: It's a critical error response, informing the manager that the requested access failed because the destination was not found.
- AXI Response Signals: AXI uses response signals to indicate the outcome of a transaction. The main responses are:
- OKAY: The transaction completed successfully.
- EXOKAY: Exclusive transaction completed successfully.
- SLVERR (Slave Error): The transaction reached a subordinate, but the subordinate encountered an error during the access (e.g., accessing a write-only register with a read transaction).
- DECERR (Decode Error): The transaction address did not map to any subordinate.
How DECERR Differs from SLVERR
It's important to distinguish DECERR from SLVERR:
- DECERR: The transaction did not reach a valid subordinate. The error is typically reported by the interconnect.
- SLVERR: The transaction reached a valid subordinate, but the subordinate itself reported an error. The error is reported by the subordinate.
| Feature | DECERR (Decode Error) | SLVERR (Slave Error) |
|---|---|---|
| Cause | Address does not map to a subordinate | Subordinate encounters an error |
| Generated By | Interconnect (typically) | Subordinate |
| Reach | Transaction doesn't reach subordinate | Transaction reaches subordinate |
| Indicates | Invalid or unmapped address | Error within a validly addressed subordinate |
Example Scenario
Imagine an AXI system with a CPU connected to an interconnect, which in turn connects to a block of RAM at address 0x1000 and a UART peripheral at 0x2000.
- If the CPU attempts to read from address
0x1004, the interconnect decodes the address, routes it to the RAM, and the RAM returns an OKAY response with the data. - If the CPU attempts to write to address
0x3000, the interconnect decodes the address and finds that0x3000does not correspond to either the RAM or the UART. The interconnect then returns a DECERR response to the CPU. - If the CPU attempts an invalid operation on the UART at
0x2000(e.g., writing more data than the buffer can hold in a single transaction, depending on the UART's implementation), the interconnect routes the transaction to the UART. The UART processes the request but might return a SLVERR if it detects an issue.
Handling DECERR
Managers (like CPUs) must be designed to handle DECERR responses. Typically, a DECERR will trigger an exception or an error flag within the manager, allowing the software or surrounding logic to identify and potentially recover from the invalid memory access.
